1. Field of the Invention
The present invention relates to semiconductor device structures and, in particular, to active area silicon island structures for use in semiconductor devices and methods for their manufacture.
2. Description of the Related Art
The manufacturing of semiconductor devices (e.g. MOS transistors, bipolar transistors, diodes, capacitors, resistors, etc.) typically involves their formation in, and on, an area of a silicon substrate that is known as the "active area silicon island" or simply "active area." An individual active area silicon island, and its associated semiconductor device(s), is customarily isolated from neighboring active area silicon islands by electrical isolation regions. A combination of an active area silicon island and its associated electrical isolation region can be designated as an active area silicon island structure. In deep sub-micron semiconductor device manufacturing, Shallow Trench Isolation (STI) processes are the most common method of forming active area silicon island structures.
In a conventional STI process, a trench with an essentially rectangular cross-section profile is first etched into a silicon substrate 10. A silicon dioxide (SiO.sub.2) layer is subsequently deposited on the silicon substrate 10 (typically using a relatively expensive high density plasma-based [HDP] technique) and planarized to form a silicon dioxide (SiO.sub.2) electrical isolation region 12 and active area silicon island 16, as shown in FIG. 1. The result of a conventional STI process is the formation of an active area silicon island structure 18 with relatively sharp corners 20, 22, 24 and 26 at the top and the bottom of the interface between the SiO.sub.2 electrical isolation region 12 and the active area silicon island 16.
The corners 20, 22, 24 and 26 are an artifact of the essentially rectangular cross-section profile of both the active area 16 and the SiO.sub.2 electrical isolation region 12. These relatively sharp corners create a high mechanical stress in the active area silicon island that can lead to a reduction in the integrity of a silicon dioxide gate subsequently grown thereon. Even if costly and time consuming procedures are implemented to (a) etch a trench with a slight sidewall angle (as a precursor to an active area with an essentially quadrilateral cross-section profile) or to (ii) lessen the sharpness of the corners 20, 22, 24 and 26 through a rounding of their profile, an undesirably high mechanical stress is still often present in active area silicon islands formed using conventional STI processes.
In addition, if the silicon dioxide layer is over-planarized, such that the upper surface of the resulting SiO.sub.2 electrical isolation region 12 is below the upper surface of the active area silicon island 16, a subsequently deposited polysilicon gate layer can "wraparound" the top corners 20 and 22 of the active area silicon island 16. This "wraparound" can result in an undesirable transistor electrical phenomena known as "double hump" and/or short circuits between neighboring semiconductor devices due to the presence of polysilicon gate layer stringers. For a further discussion of the requirements and drawbacks of conventional STI processes, see M. Nandakumar et al., Shallow Trench Isolation for Advanced ULSI CMOS Technologies, IEDM, 133-136 (1998), which is hereby fully incorporated by reference.
U.S. Pat. No. 4,698,316 to Corboy, Jr. et al. and U.S. Pat. No. 5,592,792 to Corboy, Jr. et al., both of which are hereby incorporated by reference, describe epitaxial silicon deposition methods for the formation of "silicon islands" within the apertures of a silicon dioxide masking layer. The resulting silicon islands have a rectangular cross-section profile and are, therefore, subject to an undesirably high mechanical stress in a similar manner to active area silicon island structures formed using conventional STI processes.
Still needed in the art is an active area silicon island structure with low mechanical stress that is not susceptible to polysilicon gate layer "wraparound" or polysilicon gate layer stringer formation. Also needed is a process for its manufacture that is simple, inexpensive and compatible with standard semiconductor device processing.